Electrostatic discharges (ESDs) from human handling of a metal-oxide silicon (MOS) IC chip or from other causes permanently damage the IC chip. Often the thin-oxide layer that isolates the gate electrode from the substrate of a MOS field effect transistor is irreparably ruptured by a voltage spike applied across it. A voltage spike or ESD is often applied to the gate because the gate electrode is connected to an external terminal or pin of the IC chip. The external terminals are formed on an input or output pad. To prevent such damage from excessive electrostatic discharges, a protective device is often connected between the pad and the internal circuits.
As CMOS technology is scaled down into the submicron regime, the processes and the structures, such as thinner gate oxide, shorter channel length, shallower source/drain junction, LDD(Lightly-Doped Drain) structure, and silicided diffusion, greatly degrade the ESD robustness of submicron CMOS ICs. The submicron CMOS devices, such as short channel thin-oxide MOS devices, are extremely susceptible to ESD damage. Therefore, ESD protection has become one of the most important elements with respect to the reliability of submicron CMOS ICs. The following two references discuss the degraded ESD robustness of submicron CMOS ICs.
[1] C. Duvvury and A. Amerasekera, "ESD: A Pervasive Reliability Concern for IC Technologies", Proc. of IEEE, vol. 81, no. 5, pp. 690-702, May 1993, and PA1 [2] A. Amerasekera and C. Duvvury, "The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design", 1994 EOS/ESD Syrup. Proc., EOS-16, pp. 237-245. PA1 [3] R. N. Rountree, "ESD Protection for Submicron CMOS Circuits: Issues and Solutions" 1988 IEDM Technical Digest, pp. 580-583, PA1 [4] R. N. Rountree, C. Cuvvury, T. Maki, and H. Stiegler, "A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes", 1988 EOS/ESD Symp. Proc. EOS-10, pp. 201-205, PA1 [5] C. Duvvury, T. Taylor, J. Lindgren, J. Morris, and S. Kumar, "Input Protection Design for Overall Chip Reliability", 1989 EOS/ESD Symp. Proc., EOS-11, pp. 190-197, PA1 [6] A. Chatterjee and C. Duvvury, "Efficient ESD Input Protection Scheme," U.S. Pat. No. 4,896,243, 1990. PA1 [7] G. N. Roberts, "Input ESD Protection Circuit", U.S. Pat. No. 5,336,908, 1994, and PA1 [8] R. N. Rountree, "Electrostatic Discharge Protection Circuit" U.S. Pat. No. 5,012,317 1990. PA1 [9] G. Rieck and R. Manely, "Novel ESD Protection for Advanced CMOS Output Drivers", 1989 EOS/ESD Symp. Proc., EOS-11, pp. 182-189. PA1 [10] C. Duvvury and R. Rountree, "A Synthesis of ESD Input Protection Scheme", 1991 EOS/ESD Syrup. Proc. , EOS-13, pp. 88-97, and PA1 [11] R. N. Rountree, "Circuit Structure with Enhanced Electrostatic Discharge Protection", U.S. Pat. No. 4,939,616, 1990. PA1 [12] L. R. Avery, "Voltage Stress Alterable ESD Protection Structure," U.S. Pat. No. 5,010,380, 1991. PA1 [13] L. R. Very, "SCR Protection Structure and Circuit with Reduced Trigger Voltage", U.S. Pat. No. 5,274,262, 1993, and PA1 [14] L. R. Avery, "SCR Electrostatic Discharge Protection for Integrated Circuits", U.S. Pat. NO. 5,343,053, 1994, PA1 [15] K. L. Chen and R.H. Pang, "Electrostatic Discharge Protection for Semiconductor Input Devices", U.S. Pat. No. 5,077,591, 1991, and PA1 [16] K. D. Chen and R. H. Pang, "Method to Making Electrostatic Discharge Protection for Semiconductor Input Devices", U.S. Pat. No. 5,166,089, 1992, PA1 [17] C. -Y. Wu, M. -D. Ker, C. -Y. Lee, and J. Ko, "A New On-chip ESD Protection Circuit With Dual Parasitic SCR Structures for CMOS VLSI", IEEE Journal of Solid-State Circuits, Vol. 27, No. 3, pp. 274-280, 1992, PA1 [18] M. -D. Ker, C. -Y. Lee, C. -Y. Wu, and J. Ko, "CMOS ESD Protection Circuit with Parasitic SCR Structures", U.S. Pat. No. 5,140,401, 1992, PA1 [19] M. -D. Ker, C. -Y. Wu, and C. -Y. Lee, "A Novel CMOS ESD/EOS Protection Circuit with Full -SCR Structures", 1992 EOS/ESD Symp. Proc., EOS-14, pp. 258-264, PA1 [20] M. -D. Ker, C. -Y. Lee, and C. -Y. Wu, "CMOS On-Chip ESD Protection Circuit and Semiconductor Structure", U.S. Pat. No. 5,182,220, 1993, PA1 [21] M. -D. Ker and C. -Y. Wu, "CMOS On-Chip Electrostatic Discharge Protection Circuit Using Four-SCR Structures with Low ESD-Trigger Voltage", Solid-State Electronics, Vol. 37, No. 1, pp. 17-26, 1994, and PA1 [22] M. -D. Ker and C. -Y. Wu, "CMOS On-Chip ESD Protection Circuit and Semiconductor Structure", U.S. Pat. No. 5,289,334, 1994. PA1 [23] A. Chatterjee and T. Polgreen, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, vol. 12, no. 1, pp. 21-22, Jan. 1991, and PA1 [24] A. Chatterjee and T. Polgreen, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", 1990 Proc. Symposium on VLSI Technology, pp. 75-76. PA1 (1) PS mode: ESD stress at a pin with positive voltage polarity with respect to the VSS(GND) pin when the VDD pin is floating; PA1 (2) NS mode: ESD stress at a pin with negative voltage polarity with respect to the VSS(GND) pin when the VDD pin is floating; PA1 (3) PD mode: ESD stress at a pin with positive voltage polarity with respect to the VDD pin when the VSS(GND) pin is floating; PA1 (4) ND mode: ESD stress at a pin with negative voltage polarity with respect to the VDD pin when the VSS(GND) pin is floating. PA1 [25] C. Duvvury, R. N. Rountree, and O. Adams, "Internal Chip ESD Phenomena Beyond the Protection Circuit", IEEE Trans. on Electron Devices, vol. 35, no. 12, pp. 2133-2139, Dec., 1988, PA1 [26] X. Guggenmos and R. Holzner, "A New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stress", 1991 EOS/ESD Symp. Proc., EOS-13, pp. 74-82, PA1 [27] H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the Series Resistance of On-Chip Power Supply Buses on Internal Device Failure after ESD Stress", IEEE Trans. on Electron Devices, vol. 40, no. 11, pp. 2081-2083, Nov., 1993, and PA1 [28] C. Johnson, T. J. Maloney, and S. Qawami, "Two Unusual HBM ESD Failure Mechanisms on a Mature CMOS Process", 1993 EOS/ESD Symp. Proc., EOS-15, pp. 225-231.
To improve ESD protection capability of a CMOS on-chip ESD protection circuit, a lateral semiconductor controlled rectifier (SCR) device has been used as a main ESD protection element in CMOS ICs to bypass ESD stress.
FIG 1a shows an SCR 100, often called a thyristor, which is a three terminal device having an anode 110, a cathode 120 and a gate 130. FIG 1b shows the four layer geometry of a lateral SCR device comprising a P-N-P-N structure. Normally, the SCR is off and does not conduct between its anode 110 and cathode 120. A small current i.sub.G (a few milliamps), which flows through the gate 130, initiates switching of the SCR 100 to a conducting state. A DC switching voltage VG, which is applied to the gate 130 through a resistor R.sub.G, provides the current i.sub.G. This turns on the SCR 100 and allows a large current i to flow from the anode 110 to the cathode 120.
FIG 1c shows the I-V characteristic of the SCR 100, where the vertical axis 150 represents the current i flowing from the anode 110 to the cathode 120 and the horizontal axis 160 represents the voltage v across the SCR 100 between its anode 110 and its cathode 120 as shown in FIG 1a. When the current i is reduced below a critical value, called a holding current i.sub.h, then the SCR 100 is turned off. That is, the SCR 100 is switched from the conducting state to a blocking or non-conducting state.
The DC switching voltage of a lateral SCR device in a submicron process is around 30V to about 50V as indicated in the following references:
An SCR having a switching voltage from 30 to 50 volts is inadequate to protect thin oxide CMOS devices. For example, using an approximately 0.6-0.8 .mu.m CMOS process, the gate-oxide thickness of the CMOS devices is only around 150-200 .ANG.. Such a thin gate-oxide will be damaged by a voltage of about 15 to 20 volts across it because the dielectric breakdown strength of SiO.sub.2 is about 10 MV/cm. Thus, the lateral SCR device a switching voltage of 30 V to 50 V can not protect the gate oxide of a CMOS input stage alone without additional secondary ESD protection elements.
Several of the references cited above, namely reference numbers [3] to [7], have reported designing the lateral SCR device with secondary protection elements to complete the overall ESD protection function. But, the additional secondary protection elements occupy greater layout area. This is undesirable as it prevents fabrication of compact ESD protected CMOS IC chips.
Thus, if the switching voltage of a lateral SCR device can be reduced below the gate-oxide breakdown voltage of CMOS devices, then the lateral SCR device can alone perform the sufficient ESD protection capability in a minimum layout area. In contrast, other ESD protection elements, such as diodes, thick-oxide devices, gate oxide devices, and parasitic bipolar devices in CMOS IC's do not provide such an efficient ESD protection in the smallest layout area possible.
Certain references have modified the structure of the lateral SCR device to lower its switching voltage in submicron CMOS technologies. One such reference is:
In order to lower the switching voltage of the lateral SCR device, the Rieck reference uses an oversized "NLCS" mask to make a "recessed filed threshold region" along the P-N-P-N structure of the lateral SCR device. However, this method increases both the process complexity and the difficulty of controlling the device performance.
Another lateral SCR device structure has been proposed by the following two references:
These two references [10] and [11] propose a modified lateral SCR (MLSCR) structure wherein an N.sup.+ diffusion is made across the junction edge between an N-well and a P-substrate. This lowers the switching voltage of the MLSCR device to about 23 V. However, secondary protection elements are still needed to complete the ESD protection function.
The following reference [12] proposed a voltage-stress-induced lateral SCR device.
Initially, the voltage-stress-induced lateral SCR device of Avery is not an SCR device. As its name implies, it is the voltage-stress which induces this device to behave like an SCR. That is, after a voltage-stress, this device has the I-V characteristics of an SCR device.
In the two following references [13]-[14],
a zener diode was inserted into the lateral SCR device to lower the switching voltage of the SCR. However, inserting such a zener diode requires additional and costly process steps during fabrication of this device structure by a commercial CMOS process.
In another two references [15]-[16],
a separated vertical P-N-P bipolar transistor was placed adjacent to a lateral SCR device and used to trigger the lateral SCR device. However, this bipolar-trigger lateral SCR device also needs secondary protection elements to complete its ESD protection function.
In yet other references [17]-[22], a junction capacitance was used to lower the trigger voltage of lateral SCR devices under ESD-stress conditions. Lowering the trigger voltage due the added capacitance is possible, because the ESD event is essentially a pulse-like voltage that stresses the device. By the adding a capacitance, the pulse-mode trigger voltage of the lateral SCR device can be efficiently lowered to below the gate-oxide breakdown voltage. However, a precise capacitance value is difficult to obtain, control and duplicate in different CMOS processes.
In the references [17] and [18] listed below, there are two lateral SCR structures used in the input ESD protection circuit. In the references [19]-[22] listed below, there are four lateral SCR structures used in the input ESD protection circuit to one-by-one protect against the four-mode ESD stresses.
In the references [17]-[22], a capacitance-couple effect triggers on the lateral SCR devices during an ESD voltage transition. A thick-oxide (or often referred to as a field-oxide) device is used to help the turn-on speed of each lateral SCR structure discussed in the references [17]-[22]. A suitable capacitance in each lateral SCR structure needs to be precisely designed to perform proper ESD protection. However, a precise capacitance value may under certain circumstances not be easily obtained in different CMOS processes. Therefore, the ESD protection circuits discussed in the references [17]-[22] may be difficult to use in some cases in different CMOS technologies before experimental test chips are verified in each CMOS process.
The references [17]-[22] are
In two other references [23]-[24], another modified structure of a lateral SCR device called as LVTSCR (Low-Voltage Trigger SCR) has been discussed. The two references [23]-[24] are:
FIG. 2 shows the LVTSCR device 200 connected between an input pad 205 and a CMOS input stage 210 which is to be protected from ESD. The input pad 205 (or an output pad) is connected to the anode 215 of the LVTSCR device 200. The LVTSCR device 200 is made by inserting a short-channel NMOS device 220 into the lateral SCR device.
The lateral SCR device is a P-N-P-N lateral SCR where its anode is a P+ region 215 which acts as the first P region of the P-N-P-N lateral SCR device. The P+ region 215 is diffused in an N-well 225 which acts as the first N region of the P-N-P-N lateral SCR device. The P-substrate 230 acts as the second P region while another N+ region 235, which is diffused in the P-substrate 230, acts as the second N region of the P-N-P-N lateral SCR device. The N+ region 235 acts as the cathode of lateral SCR device.
The short-channel NMOS device 220 has a drain 240 which is diffused across a junction edge between the N-well 225 and the P-substrate 230. The N+ region 235 acts as the source of the short-channel NMOS device 220. A gate 245 of the short-channel NMOS device 220 is formed on the P-substrate 230 between the source 235 and the drain 240. The gate 245 is shorted to the source 235 and connected to ground.
The LVTSCR device has a trigger voltage which is lower than the gate-oxide breakdown voltage of the CMOS devices of the input stage 210. As a high voltage occurs at the anode 215 of the LVTSCR device 200, this high voltage is diverted to the drain 240 of the short-channel NMOS device 220.
In the short-channel NMOS device 220, the snapback breakdown voltage from the drain 240 to the source 235 is generally lower than its gate-oxide breakdown voltage. In the snapback breakdown condition, the short-channel NMOS device 220 causes current to flow from the N-well 225 to the P-substrate 230. The N-well to P-substrate junction is reverse biased. Therefore, the short-channel NMOS device 220 leads to a self-regeneration turn-on action of the lateral SCR device.
After the turn-on action, the LVTSCR device can alone provide ESD protection function without additional secondary protection elements. However, the LVTSCR device reported in references [23] and [24] does not offer ESD current discharging paths from the input pad to VDD. Therefore, the devices of the internal circuits between the input pad and the VDD bus are susceptible to ESD stresses.
Since the ESD voltages at a pin may have positive or negative polarities with respect to both VDD and VSS (ground) pins, there are four different ESD stress modes at each input or output pin:
These ESD voltages and currents could damage both the NMOS and PMOS devices in the input stage or the output buffer of CMOS ICs. FIG. 3 shows a CMOS input stage 210 to be protected against excessive high voltages (see also FIG. 2).
Illustratively, the input stage 210 includes a thin-oxide PMOS device P1 and a thin-oxide NMOS device N1. The source 315 of the PMOS device P1 is connected to a VDD bus and its drain 325 is connected to the drain 330 of the NMOS device N1. The source 335 of the NMOS device N1 is connected to a VSS bus which is normally grounded. The gates 345, 350 of the PMOS and NMOS devices P1, N1 are connected together to form an input 355 of the input stage 210. This input 355 is connected to the output of an ESD protection circuit. The output of the input stage 210 is formed by the common drain connection 360. Depending on the signal applied to the input 355 of the input stage 210, the output 360 of the input stage 210 is pulled up to VDD or pulled down to VSS.
In the references [3]-[16] and [23]-[24] cited above, there is only one lateral SCR device in the ESD protection circuit. This lateral SCR device is arranged between the input (or output) pad and the VSS(GND). Thus, it provides a direct ESD path only to the VSS bus which only protects against the PS and NS ESD stress modes. There is no ESD protection element arranged between the pad (input or output) and VDD.
FIG. 4 shows a block diagram of such an arrangement, where an ESD protection circuit 410 is connected between the input pad 205 and the input stage 210.
For the PD-mode or the ND-mode, where VSS is floating, the ESD current/voltage is first diverted from the input pin 420 to the VSS power line of the CMOS IC through the pad-to-VSS ESD protection circuit 410. This ESD current/voltage flows along the VSS power line which is connected to internal circuits 430 of the CMOS IC chip. The VSS power line or bus surrounds the whole CMOS IC chip.
At some point, this ESD current/voltage flows from the VSS power line to the VDD power line through either added VDD-to-VSS ESD protection elements or through other devices connected between the VDD and VSS power lines. Now, the ESD current/voltage flows along the VDD power line to a VDD pad connected to the VDD bus which is relatively grounded. Finally, this ESD current/voltage goes out of the CMOS IC chip from the VDD pin.
Due to the parasitic resistance and capacitance along the VSS/VDD power lines in the CMOS IC chip, as well as the voltage drops on the pad-to-VSS and VDD-to-VSS ESD protection elements, such a non-direct ESD discharging path causes unexpected ESD damage to the input stage 210 and the internal circuits 430. Therefore, without a direct ESD discharging path from the pad 205 to the VDD bus, the ESD protection circuit 410 cannot fully protect the input stage 210 and the internal circuits 430. Unexpected ESD damage occurs especially if the die size of the whole IC chip is large. This problem is discussed in the following references:
It is the object of the present invention to provide an ESD protection circuit which provides a full protection for submicron CMOS technology by providing direct ESD discharging paths from the input and output pads to both the VDD and VSS power lines.
It is another object of the present invention to lower the turn-on voltage of a lateral SCR and to trigger on the lateral SCR by the inserted short-channel NMOS or PMOS devices at the snapback breakdown condition.
It is yet another object of the present invention to provide a robust ESD protection circuit which has sufficient ESD current discharging paths to shunt large ESD currents.
Another object of the present invention is to reduce the layout area needed for the ESD protection circuits thus reducing the size and cost of the IC chips and increasing packing density.
A further object of the present invention is to provide such an ESD protection without adversely affecting the operation of the internal circuits which are being protected, such as maintaining reliability and speed of operation of the internal circuits. Another object is to provide a voltage clamping effect on the input signals provided to the internal circuits to be protected.